The present invention relates to semiconductor integrated circuits and, more particularly, to a memory structure and an operate method suitable for a memory which needs operating at high-speed operating cycle time.
The present invention further relates to a memory LSI suitable for use in a pipelined memory incorporating a plurality of latch circuits in a memory chip and to a digital system using such a memory LSI.
There are known techniques of providing latch circuits in circuit blocks of a memory LSI chip: Japanese Patent Laid-Open No. 128097/1983 discloses the art of using address and clock signal buffers as latch circuits.
Japanese Patent Laid-Open No. 250584/1987 discloses the art of increasing a read cycle speed by controlling latch timing of respective latch circuits provided in an address latch circuit and an output data latch circuit.
Japanese Patents Laid-Open Nos. 250583/1987, 70996/1988 disclose the art of increasing a write cycle speed by providing an address latch circuit and a latch circuit for latching a write control signal.
However, all of the aforementioned prior arts are incapable of providing a read cycle time that is far shorter than the delay time (i.e. access time) of a signal from an address latch circuit up to an output data latch circuit and of providing a write cycle time that is far shorter than the sum of the delay time of a signal from a latch circuit for latching a write control signal up to a memory cell and the switching time of the memory cell.